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Posted: **Wed May 20, 2009 3:16 am**

Has onyone had any success figuring out these SMODE1, SYNCH1, SYNCH2, SYNCV GS registers? At least some partial information regarding what parts of sync timings do these bits correspond to.

Posted: **Wed May 20, 2009 4:16 am**

Does this help?

Code: Select all

#define GS_S_SMODE1_REG         MIPS_PHYS_TO_KSEG1&#40;0x12000010&#41;
#define GS_S_SYNCH1_REG         MIPS_PHYS_TO_KSEG1&#40;0x12000040&#41;
#define GS_S_SYNCH2_REG         MIPS_PHYS_TO_KSEG1&#40;0x12000050&#41;
#define GS_S_SYNCV_REG          MIPS_PHYS_TO_KSEG1&#40;0x12000060&#41;

#define SMODE1&#40;vhp, vcksel, slck2, nvck, clksel, pevs, pehs, pvs, phs,  \
    gcont, spml, pck2, xpck, sint, prst, ex, cmod, slck, t1248, lc, rc&#41; \
        &#40;&#40;&#40;u_int64_t&#41;&#40;vhp&#41;      << 36&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;vcksel&#41;    << 34&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;slck2&#41;     << 33&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;nvck&#41;      << 32&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;clksel&#41;    << 30&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;pevs&#41;      << 29&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;pehs&#41;      << 28&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;pvs&#41;       << 27&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;phs&#41;       << 26&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;gcont&#41;     << 25&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;spml&#41;      << 21&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;pck2&#41;      << 19&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;xpck&#41;      << 18&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;sint&#41;      << 17&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;prst&#41;      << 16&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;ex&#41;        << 15&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;cmod&#41;      << 13&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;slck&#41;      << 12&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;t1248&#41;     << 10&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;lc&#41;        <<  3&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;rc&#41;        <<  0&#41;&#41;

#define SYNCH1&#40;hs, hsvs, hseq, hbp, hfp&#41;                                \
        &#40;&#40;&#40;u_int64_t&#41;&#40;hs&#41;       << 43&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;hsvs&#41;      << 32&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;hseq&#41;      << 22&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;hbp&#41;       << 11&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;hfp&#41;       << 0&#41;&#41;

#define SYNCH2&#40;hb, hf&#41;                                                  \
        &#40;&#40;&#40;u_int64_t&#41;&#40;hb&#41;       << 11&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;hf&#41;        << 0&#41;&#41;

#define SYNCV&#40;vs, vdp, vbpe, vbp, vfpe, vfp&#41;                            \
        &#40;&#40;&#40;u_int64_t&#41;&#40;vs&#41;       << 53&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;vdp&#41;       << 42&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;vbpe&#41;      << 32&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;vbp&#41;       << 20&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;vfpe&#41;      << 10&#41; |                                \
        &#40;&#40;u_int64_t&#41;&#40;vfp&#41;       << 0&#41;&#41;

source: http://www.google.com/codesearch/p?#2HK ... ee/gsreg.h

Posted: **Wed May 20, 2009 4:44 am**

Thanks, but I have already got that info from http://playstation2-linux.com/ however these aren't of much use as I can't decipher those abbreviations to human readable terms like Sync pulse length and so on.

What I'm trying to achieve here is to add a 24p/i mode so SMS wouldn't produce jerks every second on a 24fps video.

Posted: **Wed May 20, 2009 7:08 am**

Having 24p support would be great! But there are other ways to make 24p look good on 50i or 60i (without jerks).
- Using a "3:2 pulldown" you could display the video at 60i.
- Or by increasing the speed of the video to 25fps you could display it at 50i/25p.

Posted: **Wed May 20, 2009 7:22 am**

- "3:2 pulldown" - absolutely horrible results I even wonder how people from NTSC countries bear watching movies at home
- 25 fps speedup patch is already made by some guy from psx-scene and sent to EEUG

However I'm just curious about finding a way to produce a 24/48Hz signal from GS. And that would be a cleanear solution than resampling the audio.

Posted: **Wed May 20, 2009 10:33 am**

uufyugi wrote:However I'm just curious about finding a way to produce a 24/48Hz signal from GS. And that would be a cleanear solution than resampling the audio.

I'm curious if any TVs would accept this, as far as I know the only "supported" 24fps mode is over HDMI. If you interlaced it at 48hz (24 frames) maybe some PAL TVs would accept it as "off standard" since it's quite close. Of course multiscan PC monitors might accept it if you enable the Sync-on-Green sync multiplexer. (although 48hz vertical might be too slow, maybe 72Hz if you're targeting these?)

The best way to do new modes for PS2 is to get an oscilloscope and connect to green or composite channel (depending on where the sync pulses are). Most of the registers should be pretty obvious if you know about video timing.

Also remember that the sync chip changed at some point so to support all PS2s you'll need to create modes for all variations,

Posted: **Wed May 20, 2009 7:49 pm**

jbit wrote:If you interlaced it at 48hz (24 frames) maybe some PAL TVs would accept it as "off standard" since it's quite close.

Yes I'm hoping for that.

jbit wrote:Most of the registers should be pretty obvious if you know about video timing.

I'd say that some are somehow decipherable.
If anyone has any information regarding even one of these - please share. The less would be there left the less I would have to deduce.

Posted: **Wed May 20, 2009 8:10 pm**

Try looking at the PS2 linux video driver.

Posted: **Thu May 21, 2009 1:35 am**

The good news
- the SYNCH/SYNCV registers aren't rocket science so it's no big deal figuring these out
- a SD multisystem tv set syncs just fine to 47.9462 Hz (the closest I got to 47.9520) no smoke or funny noises

The bad news
- I don't have an oscilloscope so I can't check if all the pulses are where they should be so I'm not very comfortable with leaving the tv set in that mode for prolonged periods

So
- Is there anyone willing to help me and check that with an oscilloscope?
- yet got to check how that would work with SMS

Posted: **Thu May 21, 2009 2:53 am**

Good news indeed! I don't have an oscilloscope but I can test it on 2 tv's if you like.

I'm sure more people will be interested in those registers, so if you decipher them, could you share the "human readable terms".

Posted: **Thu May 21, 2009 5:01 am**

Maximus32 wrote:I can test it on 2 tv's if you like.

Sure. I'll upload some test program in a while.

Maximus32 wrote:I'm sure more people will be interested in those registers, so if you decipher them, could you share the "human readable terms".

I have no idea. They do look somehow familiar like fpe = front porch end and the like but it's of no much use without knowing where these timings are calculated from.
I just changed them cautiously, noticing the changes and calculating the vertical frequency. And I'm still not quite sure that everything is right.

ATM I'm just glad that the tv set syncs to the required signal and will proceed with experiments.

Posted: **Fri Oct 09, 2009 2:47 pm**

Guys,
Do you make any progress here?
If so, could you share with us?
Tks in advance!

Posted: **Thu Oct 15, 2009 9:40 pm**

No response yet... But okay, no problem... Anyway...

@all,

We made some progress on this subject...!

Are you interested? If so, get further info on "GS Mode Selector: Development & Feedback" (http://www.psx-scene.com/forums/showthread.php?t=61808) thread on PSX-SCENE.

You are invited to visit, sign in, and join us!

BR,

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SMODE1 question

SMODE1 question