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[SilverSpring]

In psppower.h, prototype is this:

/**
* Set Clock Frequencies
*
* NOTE: Please use scePowerSetBusClockFrequency and
* scePowerSetCpuClockFrequency instead of this function
* for clock <= 222 and bus <= 111.
*
* @param cpufreq - cpu frequency, valid from 1-333
* @param ramfreq - ram frequency, valid from 1-333
* @param busfreq - bus frequency, valid from 1-166
*/
int scePowerSetClockFrequency(int cpufreq, int ramfreq, int busfreq);

I think should be:

/**
* Set Clock Frequencies
*
* @param pllfreq - pll frequency, valid from 19-333
* @param cpufreq - cpu frequency, valid from 1-333
* @param busfreq - bus frequency, valid from 1-167
*
* and:
*
* cpufreq <= pllfreq
* busfreq*2 <= pllfreq
*
*/
int scePowerSetClockFrequency(int pllfreq, int cpufreq, int busfreq);

[SilverSpring]

Just to confirm:

scePowerGetPllClockFrequencyInt()
scePowerGetCpuClockFrequencyInt()
scePowerGetBusClockFrequencyInt()

does in fact return the 1st, 2nd, & 3rd arguments of

scePowerSetClockFrequency(pllfreq, cpufreq, busfreq);


eg.

setting scePowerSetClockFrequency(333, 266, 111);

then,

scePowerGetPllClockFrequencyInt() returned 333
scePowerGetCpuClockFrequencyInt() returned 265
scePowerGetBusClockFrequencyInt() returned 110

Thus the prototype should be changed accordingly, as per above post.

[jimparis]

I applied the changes manually, thanks.
In the future a patch (from "svn diff") is preferred.

[Saotome]

does this mean that this:

[SilverSpring]

The pllfreq is what the cpu & bus freq is derived from. Its based on a ratio of x/511 of the pllfreq. Thats why even trying to set a definite freq eg. scePowerSetClockFrequency(333, 266, 111), cpu & bus wont return that exact frequency.

cpufreq will actually return (approx) 265.89 (which is 408/511 times pllfreq)
busfreq*2 will actually return (appox) 221.57 (which is 340/511 times pllfreq)

The ratio is stored 0xBC200000 for cpu & 0xBC200004 for bus (numerator is 1st 9 bits of upper halfword, denominator is 1st 9 bits of lower halfword).

You can get the ratio's with these:

// Get cpufreq ratio
int sceSysreg_driver_44704E1D(int *numerator, int *denominator);

// get busfreq ratio
int sceSysreg_driver_377F035F(int *numerator, int *denominator);

or set ratio:

// Set cpufreq by ratio
// both values have to between 1-511
// obviously numerator cant be greater than denominator
// eg. sceSysreg_driver_5664F8B5(511, 511) gives 100% of pllfreq
int sceSysreg_driver_5664F8B5(int numerator, int denominator);

// set busfreq ratio
int sceSysreg_driver_584AD989(int numerator, int denominator);

or set/get freq by float value:

// Set cpufreq by float
// Will set to nearest granuality
// eg. sceSysreg_drver_AB3185FD(200.0) will only give 199.84 (460/511 = 90.02% of default pllfreq (222))
int sceSysreg_drver_AB3185FD(float cpufreq);

// Get cpufreq
float sceSysreg_driver_0EA487FA(void);

// set busfreq
int sceSysreg_driver_136E8F5A(float busfreq);

// get busfreq
float sceSysreg_driver_F4811E00(void);


Thats about all I know....

[hlide]

i knew it , i knew it ! thanx for your confirmation XD

[crazyc]

It seems, from some quick testing, that the media engine cpu frequency is equal to the pll frequency.

[hlide]

[J.F.]

[dot_blank]

i am so glad this is finally confirmed :) great job SS
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[crazyc]

[hlide]

how do you measure the difference on SC and ME processors ? because I don't see any good way to do so. you'd probably need to let SC and ME processors to read their own COP0 Count register, preferrably without any interrupts.

SC processor side :

[J.F.]

[crazyc]

[hlide]

huh, beware that an access to memory switchs CPU frequency to BUS frequency temporary so you should avoid having a different code when running on SC and ME processors (not speaking about miss cache too).

So you should really have the same code running a certain time as I showed above without any call to external functions for instance.

EDIT:

i read somewhere that instructions like lb/lbu/lh/lhu/lw/lwl/lwr/sb/sh/sw/swl/swr runs at bus frequency and not at cpu frequency. So if you have 63 cycles for a lw instruction (miss-cache), it doesn't mean 63 cycles at 333 MHz but rather at 166 MHz.

[crazyc]

[sakya]

Hi! :)

I'm not able to set the bus clock to 14Mhz (or anithing less than 37Mhz != 9Mhz).
Can someone help me?
Reading here and also here http://lan.st/archive/index.php/t-854.html that's what I tried:

If I do:

[SilverSpring]

Im pretty sure the reason why you cannot go lower than 37MHz is because the PLL basefreq is 37MHz, so that is as low as you can go. Trying to go lower will cause funny effects.
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[crazyc]